LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
library simprim;

ENTITY tbProcesseurEtRom is
END tbProcesseurEtRom;

ARCHITECTURE behavior OF tbProcesseurEtRom is 


  component ProcesseurEtRom
    Port (
      CLK : in  STD_LOGIC;
      RESET : in  STD_LOGIC;
      PIN : in  std_logic_vector(3 downto 0);
      POUT : out  std_logic_vector(7 downto 0)
      );
  end component;

  signal CLK  :  STD_LOGIC:='0';
  signal RESET  :  STD_LOGIC;
  signal PIN  :  std_logic_vector(3 downto 0);
  signal POUT  :  std_logic_vector(7 downto 0);
 
  
begin


  UUT: ProcesseurEtRom
    Port map(
      CLK => CLK ,
      RESET => RESET ,
      PIN => PIN ,
      POUT => POUT
      );

  reset <= '1', '0' after 431 ns;
  
 -- IR <= sIR;
--ERd <= sERd;
--LDPC <= sLDPC;
--sPC <= ssPC;
--SUAL <= sSUAL;

  process 
  begin
    CLK<='1';
    wait for 20 ns;
    CLK<='0';
    wait for 20 ns;
  end process;

  
  tb : PROCESS
  BEGIN
   -- RESET<='1';
    wait for 100 ns;
  --  RESET<='0';
    wait for 100 ns;
    -- PIN<="1000";
    -- Place stimulus here

    wait; -- will wait forever
  END PROCESS;

END;
